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YNV05T06 DC-DC Converter Data Sheet
3.0-5.5 VDC Input; 0.7525-3.63 VDC Programmable @ 6A
Operation
Input and Output Impedance
The YNV05T06 converter should be connected via
a low impedance to the DC power source. In many
applications, the inductance associated with the
distribution from the power source to the input of
Fig. A : Input Voltage Ripple, C IN = 4x47 μ F ceramic
60
50
40
30
the converter can affect the stability of the
converter. It is recommended to use decoupling
capacitors (minimum 47 μ F) placed as close as
possible to the converter input pins in order to
ensure stability of the converter and reduce input
ripple voltage. Internally, the Converter has 20 μ F
20
10
0
0
1
2
Vout [V]
Vin=5.0V
Vin=3.3V
3
4
of Low ESR Ceramic Capacitance on board.
In a typical application, low ESR tantalum or POS
capacitors (with sufficient ripple current rating)
would be sufficient to provide adequate ripple
voltage attenuation at the input of the converter.
However, very low ESR ceramic capacitors 47 μ F-
100 μ F are recommended at the input of the
converter in order to minimize the input ripple
voltage. They should be placed as close as
possible to the input pins of the converter.
YNV05T06 has been designed for stable operation
with or without external capacitance. Low ESR
ceramic capacitors placed as close as possible to
the load (Min 47 μ F) are recommended for
improved transient performance and lower output
voltage ripple.
It is important to keep low resistance and low
inductance PCB traces when connecting the load
to the output pins of the converter. This is
Fig. B : Input Voltage Ripple, C IN = 470 μ F polymer +
2x47 μ F ceramic
Fig. A shows input voltage ripple for various output
voltages using four 47 μ F input ceramic capacitors.
The same plot is shown in Fig. B with one 470 μ F
polymer capacitor (6TPB470M from Sanyo) in
parallel with two 47 μ F ceramic capacitors at 5A
load.
ON/OFF (Pin 5)
The ON/OFF pin (Pin 5) is used to turn the power
converter on or off remotely via a system signal
that is referenced to GND (Pin 3). Typical
connections are shown in Fig. C.
To turn the converter on the ON/OFF pin should
be at a logic low or left open, and to turn the
converter off the ON/OFF pin should be at a logic
high or connected to Vin.
required to maintain good load regulation since the
converter does not have a SENSE pin for
compensating voltage drops associated with the
power distribution system on your PCB.
ON/OFF pin is internally pulled-down. A TTL or
16
CMOS logic gate, open collector (open drain)
14
12
10
8
6
4
2
Vin=5.0V
Vin=3.3V
transistor can be used to drive ON/OFF pin. When
using open collector (open drain) transistor, add a
pull-up resistor (R*) of 10K to Vin as shown in Fig.
C. External pull-up resistor (R*) can be increased
to 20K if minimum input voltage is more than 4.5V.
This device must be capable of:
0
0
1
2
Vout [V]
3
4
- sinking up to 0.6 mA at a low level voltage of
? 0.8 V
- sourcing up to 0.25 mA at a high logic level of
2.3V – 5.5V.
MCD10197 Rev. 1.0, 21-Jun-10
Page 5 of 25
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